Senior RTL Design Lead
HCLTech
Candidates with 5 to 7 years experience is mandatory
Experience in Full chip RTL integration is preferred
Experience with ASIC/SoC development flow including synthesis/timing constraints development,
Static Timing Analysis closure, resolving P& R congestion issues etc.Β
Experience in RTL Synthesis
Scripting experience
Experience integrating IP's like PCIe, USB, Ethernet etc.
Should be able to lead a team of 2 to 3 Entry Level engineersΒ
You'll be redirected to HCLTech's official application page on successfactors.