Senior Design Lead - Design Validation

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πŸ“ Chennai, India

About this role

Job Summary

Define ASIC/SoC verification strategy
Full chip testplan development
Full chip TB Architecture definition
UVM based testbench development
SV functional coverage, Assertions coding
C based TB development
Test case development, coding, execution, bug analysis
Gate Level Simulation
Regressions, coverage analysis
participate in verification closure

Key Responsibilities

Good understanding of ASIC/SoC life cycle
Has participated in multiple ASIC/SoC verification till Β tapeout stage
Experience writing ASIC/SoC testplans
"1.Experience in ASIC/SoC Testbench definition
2.Experience to Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and the Universal Verification Methodology (UVM)."
"1.Expertise & hands-on experience in OVM/UVM methodologies using SV
2.Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans."
"1. Experience in developing TB components for SOC with C, SV
"
"1. Experience in developing TB components, including functional coverage implementation and assertion coding
2. Experience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics to identify untested gaps in the design logic.
3.Debug complex simulation failures using waveform viewer tools to isolate design bugs from testbench issues.
4. Experince in SOC C based tests coding & debugging"
"Experience in Gate level simulation & netlist debugging
"
"Exeprince in regression failure analayiss
Functioncal and Code Coverage closure"
Experience in Perl/Shell scripting

Skill Requirements

Languages: Proficiency in Verilog, SystemVerilog, and core concepts of UVM.
Digital Logic: Strong foundational knowledge in digital logic design, finite state machines (FSM), FIFO architectures, and clocking concepts.Β 

EDA Tools: Familiarity with industry-standard simulation and debugging tools (e.g., Synopsys VCS, Siemens QuestaSim, Cadence Xcelium/Verdi).Β 
"Protocols:Β 

Deep, authoritative knowledge of high-speed protocols (e.g., SPI, I2C,PCIe, NVMe, Ethernet, USB) or complex bus architectures (e.g., AMBA AXI/CHI/ACE)."
Scripting: Basic comfort working in a Linux environment and using scripting languages like Python, Tcl, or Perl for automation.

Other Requirements

Education Degree:

" Bachelor's or Master's degree in Electronics & Communication Engineering (ECE),Β 
Electrical Engineering (EE), VLSI Design, or a closely related field"

Frequently Asked Questions

Is the salary disclosed for the Senior Design Lead - Design Validation position at HCLTech?
The salary for this Senior Design Lead - Design Validation role at HCLTech is not publicly listed. Click "Apply Now" to learn more about the compensation package on their official careers page.
Where is the Senior Design Lead - Design Validation position at HCLTech located?
This Senior Design Lead - Design Validation role at HCLTech is based in Chennai, India. The position is listed as on-site or hybrid. Check the full job description or apply directly to confirm the work arrangement.
How do I apply for the Senior Design Lead - Design Validation position at HCLTech?
Click the "Apply Now" button on this page. You will be redirected to HCLTech's official application portal hosted on successfactors where you can submit your application directly.
When was the Senior Design Lead - Design Validation job at HCLTech posted?
This Senior Design Lead - Design Validation position at HCLTech was posted on Sep 7, 2026. Apply as soon as possible β€” early applications are often reviewed first.
Senior Design Lead - Design Validation
HCLTech
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