The Role and Impact  

  You will be part of a highly skilled, agile design/verification team developing cutting-edge hardware for the NIC, IPU and AI domains. 

As an IP Design Verification Engineer, you will play a crucial role in ensuring the functionality and reliability of complex designs. You will develop verification plans, create test benches, and build environments to thoroughly validate meaningful parts of the chip — complex IPs and subsystems. 

Your work will directly contribute to identifying and resolving bugs in the pre-silicon environment using simulation and/or Formal Property Verification techniques, ensuring robust designs that meet high-performance standards. 

We are intentional, fast adopters of AI as a working tool. We bring modern AI assistants and automation into every part of the verification flow — planning, stimulus and checker development, coverage analysis, debug and more. 

Business group  
You will be joining Intel's Central Engineering Group (CEG), a global organization responsible for designing and verifying industry-leading IPs and architectures that power Intel's NIC, IPU and ASIC products. The group produces innovative technologies and solutions for hyperscalers, cloud providers, networking, AI and other specialized workloads. 

As part of this dynamic team, you will contribute to Intel's commitment to advancing silicon and system innovation.  
 
Key Responsibilities  
- Develop and execute IP verification plans, ensuring thorough coverage of microarchitecture specifications.  
- Design and implement test benches and verification environments to validate functionality and reliability.  
- Utilize AI and simulation models to analyze power, timing, and uncover bugs.  
- Debug, identify root causes, and implement corrective measures for failing tests in the pre-silicon environment.  
- Collaborate closely with architects, designers, DFT, and emulation/bring-up  teams to ensure correctness from block to system level. 
- Maintain and improve existing functional verification methodologies and infrastructure.  
- Document test plans, participate in technical reviews, and drive verification improvements. 

Minimum Qualifications  

- Bachelor's degree in electrical engineering, Computer Engineering, Computer Science, or related fields.  

- 5+ years of experience in functional design verification of ASIC, SOC or FPGA designs with expertise in System Verilog, OVM/UVM, and debugging tools.  

- Proficiency in creating IP test environments and/or using formal verification methods 

- Strong knowledge of digital design fundamentals and microarchitecture principles.  

Preferred Qualifications  

- Master's or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field with relevant experience in design verification.  

- Experience with formal property verification, System Verilog Assertions, code and functional coverage implementation and analysis 

- Experience collaborating across teams to drive architectural improvements.  

- Use of AI tools would be an advantage. At a minimum, require someone that is passionate about performing Pre-Silicon DV harnessing the power of AI. 

- Experience with switching/routing and communications protocols such as Ethernet, and Cryptographic Protocols such IPSec, DTLS and MACSec. 

- Experience with AMBA protocols such as APB and AXI. 

- Experience with languages such as SystemC, Python, Perl, Shell scripting and how AI can be used to integrate these in verification flows. 

We invite you to bring your expertise and enthusiasm to a team where your contributions will drive technological progress and create opportunities for impactful learning and growth.