CIASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |8-12 years| Pune)ciscoFull time☆SaveView & Apply→
CIASIC Engineering Digital Designer/ Leader ( digital design, FSM, CPU sub-systems, complex SOCs, FPGA validation | 8-12 Years | Pune)ciscoFull time☆SaveView & Apply→
CIASIC Engineering Digital Design Leader ( digital design, FSM, CPU sub-systems, complex SOCs, FPGA validation | 12-16 Years | Pune)ciscoFull time☆SaveView & Apply→