Bilingual Semiconductor Technical Lead

We are looking for an experienced Bilingual Semiconductor Technical Lead to support advanced SoC implementation projects in Japan. This is a customer-facing technical leadership role where you will work closely with clients while coordinating global engineering teams to deliver high-quality semiconductor implementation projects. The ideal candidate will act as the technical lead, working directly with customers in Japan while coordinating global engineering teams.This position requires strong expertise across the RTL-to-GDSII implementation flow, with particular focus on synthesis, timing closure, sign-off, and tape-out activities. Work Place: Tokyo, Japan Work Style: Onsite Key Responsibilities: Act as the primary technical lead for customer-facing projects. Lead technical discussions with customers and internal engineering teams. Coordinate onsite and offshore engineering resources. Drive RTL-to-GDSII implementation activities. Support synthesis, timing closure, sign-off, and tape-out execution. Drive Performance, Power, and Area (PPA) optimization. Identify technical risks and implementation bottlenecks. Collaborate closely with RTL, Physical Design, DFT, Verification, and EDA teams. Track project milestones and support successful project delivery. Requirements Essential Skills/Experience: 8+ years of semiconductor design and implementation experience. Strong understanding of the complete RTL-to-GDSII implementation flow. Hands-on experience in Synthesis, Static Timing Analysis (STA), Timing Closure, Signoff Methodology, and Tapeout activities. Experience with tools such as Design Compiler, Fusion Compiler, PrimeTime, SDC Constraint Development, Logic Equivalence Check (LEC). Strong understanding of how RTL decisions impact such as Timing, Power, Congestion, Testability, Physical Implementation. Experience leading technical teams or project delivery activities. Customer-facing communication and stakeholder management skills Business-level Japanese and English. Preferred Skills/Experience: ICC2 StarRC VC SpyGlass Floorplanning Place & Route (PnR) Clock Tree Synthesis (CTS) DRC/LVS Low Power Design Advanced-node implementation experience