Sr Principal ASIC / RTL Design Engineer
About this role
We are seeking a skilled and motivated Senior Digital IC Design Engineer with over 5 years of experience in digital design and proven expertise in memory IP integration (SRAM, ROM, EEPROM, OTP/NVM). The candidate will play a key role in the development, integration, and verification of memory subsystems in advanced SoC platforms.
- Own and drive the integration of memory IPs into larger digital subsystems and SoC platforms.
- Collaborate with memory IP teams to understand interface requirements, timing constraints, and test features.
- Perform RTL design, lint, CDC, and synthesis for digital logic blocks interacting with embedded memories.
- Define and execute design verification plans in coordination with the verification team.
- Interface with physical design and validation teams to ensure successful implementation and bring-up.
- Support post-silicon debug for memory interface-related issues.
- Contribute to technical reviews, architecture discussions, and documentation of design flows
Soft Skills
- Strong communication and documentation skills.
- Collaborative and proactive problem solver.
- Capable of mentoring junior engineers and participating in design reviews.
- Bachelor’s or Master’s degree in Electrical Engineering or related field.
- 5 years of experience in digital ASIC design, preferably with a focus on memory IP integration.
- Strong RTL design skills in Verilog/SystemVerilog.
- Proficient in EDA tools for synthesis, lint, and static timing analysis.
onsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.
More details about our company benefits can be found here:
Frequently Asked Questions
Is the salary disclosed for the Sr Principal ASIC / RTL Design Engineer position at onsemi?
The salary for this Sr Principal ASIC / RTL Design Engineer role at onsemi is not publicly listed. Click "Apply Now" to learn more about the compensation package on their official careers page.
Where is the Sr Principal ASIC / RTL Design Engineer position at onsemi located?
This Sr Principal ASIC / RTL Design Engineer role at onsemi is based in Brno, South Moravia, Czech Republic. The position is listed as on-site or hybrid. Check the full job description or apply directly to confirm the work arrangement.
Is the Sr Principal ASIC / RTL Design Engineer role at onsemi full-time or part-time?
This is listed as a Full time position. It is posted as a Sr Principal ASIC / RTL Design Engineer role at onsemi.
How do I apply for the Sr Principal ASIC / RTL Design Engineer position at onsemi?
Click the "Apply Now" button on this page. You will be redirected to onsemi's official application portal hosted on oraclecloud where you can submit your application directly.
When was the Sr Principal ASIC / RTL Design Engineer job at onsemi posted?
This Sr Principal ASIC / RTL Design Engineer position at onsemi was posted on Jul 20, 2026. Apply as soon as possible — early applications are often reviewed first.
Sr Principal ASIC / RTL Design Engineer
onsemi
You'll be redirected to onsemi's official application page on oraclecloud.