SMTS ASIC Digital Design

globalfoundries· MIPS Holding Inc
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📍 Austin📍 NetherlandsFull time

About this role

About GlobalFoundries:

GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com.


Summary of Role:

You will join the Functional Safety & Cyber Security team within GlobalFoundries' IP, Software & Custom Silicon organization, working on safety architecture and safety analysis for our ARC MIPS processor IP.

Our processor cores are certified to ISO 26262 and ship inside production automotive systems — radar, ADAS and control applications — at ASIL-B and ASIL-D. You will own the hardware safety analysis for these products, contribute to the design of safety mechanisms, and defend that work in front of automotive customers and third-party assessors.

 

Beyond processor IP, you will also cover safety for Custom Silicon SoC programs, where safety analysis spans multiple IP blocks, their integration, and system-level safety mechanisms. This part of the scope is growing, and you will help shape how we approach SoC-level functional safety.

Essential Responsibilities:

  • Own hardware safety analysis for processor IP configurations: FMEDA, DFMEA, DFA and FTA, through to external assessment.
  • Perform SoC-level safety analysis for Custom Silicon programs: integration of safety elements, system-level FMEDA, and the safety concept at the SoC boundary.
  • Analyze dependent failures and freedom from interference across IP boundaries within an SoC.
  • Derive and track safety metrics (SPFM, LFM, PMHF) and drive diagnostic coverage improvement together with the STL and verification teams.
  • Define and review safety mechanisms at RTL level — ECC, parity, lockstep, register protection, watchdog — and verify they meet the claimed diagnostic coverage.
  • Plan and interpret fault injection campaigns, and reconcile fault simulation results against the FMEDA.
  • Produce and maintain safety work products: safety manual, safety analysis reports, safety case contributions, and assumptions of use.
  • Maintain traceability from safety requirements through design to verification evidence.
  • Support ISO 26262 assessments and respond to customer technical questions on safety architecture and analysis.

Other Responsibilities:

  • Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.

Required Qualifications:

  • Master's or Bachelor's degree in Electrical/Electronic Engineering, Computer Engineering or a related field.
  • 8+ years of ASIC/SoC design or verification experience, with substantial time spent on functional safety.
  • Understanding of FMEDA, DFMEA and DFA for complex digital IP.
  • Understanding with SoC-level integration and system-level safety concepts.
  • Ability to read and analyze RTL (Verilog/SystemVerilog) and reason about microarchitecture — pipelines, caches, register files, memories.
  • Understanding of processor architecture, and how safety mechanisms are realized within it.
  • Familiarity with synthesis and DFT results as inputs to safety analysis (area back-annotation, test coverage).
  • Strong debugging and troubleshooting skills.
  • Excellent communication skills, autonomy, and the ability to run several activities in parallel.


Preferred Qualifications:

  • Functional safety certification or formal training (ISO 26262 / IEC 61508).
  • Experience as a Safety Element out of Context (SEooC) supplier, or integrating SEooC IP into an SoC safety concept.
  • Fault simulation tooling (VC Z01X or equivalent) — we will train you on our specific flow.
  • Scripting and automation (Python, TCL) — our FMEDA flow is script-driven.
  • Simulation and debug tools (VCS, Verdi); FPGA design flow.
  • Requirements management tooling (Jama) and safety traceability practice.
  • Low-power design and UPF.
  • ISO/SAE 21434 cybersecurity, or IEC 61508 in industrial applications.
  • Experience with automotive tier-one customers.
  • RISC-V architecture.

Expected Salary Range

The exact Salary will be determined based on qualifications, experience and location.

If you need a reasonable accommodation for any part of the employment process, please contact us by email at usaccommodations@gf.com and let us know the nature of your request and your contact information. Requests for accommodation will be considered on a case-by-case basis. Please note that only inquiries concerning a request for reasonable accommodation will be responded to from this email address. 

 

An offer with GlobalFoundries is conditioned upon the successful completion of pre-employment conditions, as applicable, and subject to applicable laws and regulations. 

 

GlobalFoundries is fully committed to equal opportunity in the workplace and believes that cultural diversity within the company enhances its business potential. GlobalFoundries goal of excellence in business necessitates the attraction and retention of highly qualified people. Artificial barriers and stereotypic biases detract from this objective and may be illegally discriminatory. 

 

All policies and processes which pertain to employees including recruitment, selection, training, utilization, promotion, compensation, benefits, extracurricular programs, and termination are created and implemented without regard to age, ethnicity, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, sexual orientation, gender identity or expression, veteran status, or any other characteristic or category specified by local, state or federal law 

Frequently Asked Questions

Is the salary disclosed for the SMTS ASIC Digital Design position at globalfoundries?
The salary for this SMTS ASIC Digital Design role at globalfoundries is not publicly listed. Click "Apply Now" to learn more about the compensation package on their official careers page.
Where is the SMTS ASIC Digital Design position at globalfoundries located?
This SMTS ASIC Digital Design role at globalfoundries is based in Austin, Netherlands. The position is listed as on-site or hybrid. Check the full job description or apply directly to confirm the work arrangement.
Is the SMTS ASIC Digital Design role at globalfoundries full-time or part-time?
This is listed as a Full time position. It is posted as a SMTS ASIC Digital Design role in the MIPS Holding Inc department at globalfoundries.
Which team or department does the SMTS ASIC Digital Design at globalfoundries belong to?
This SMTS ASIC Digital Design position is part of the MIPS Holding Inc department at globalfoundries. See the full job description for more information about the team structure and responsibilities.
How do I apply for the SMTS ASIC Digital Design position at globalfoundries?
Click the "Apply Now" button on this page. You will be redirected to globalfoundries's official application portal hosted on workday where you can submit your application directly.
When was the SMTS ASIC Digital Design job at globalfoundries posted?
This SMTS ASIC Digital Design position at globalfoundries was posted on Oct 9, 2026. Apply as soon as possible — early applications are often reviewed first.
SMTS ASIC Digital Design
globalfoundries
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