Senior Technical Architect

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📍 Bangalore, India

About this role

Job Summary

Position Summary

We are seeking a Firmware Engineer to design, develop, and validate embedded firmware for our Ultra-Wideband (UWB) wireless SoC platform. This role owns low-level driver development, PHY/MAC firmware bring-up, and RTOS-based application integration for UWB ranging, positioning, and sensing products built on the IEEE 802.15.4 UWB standard family. The ideal candidate combines strong embedded systems fundamentals with hands-on wireless connectivity irmware experience.

Required Qualifications

  • Minimum 5+ years of professional experience working in an embedded environment. Bachelor’s/Master’s degree (B.Tech/B.E/M.Tech/MS) in Electrical/Electronics/Computer Science/Computer Engineering or related field.
  • Strong proficiency in C for resource-constrained embedded systems; solid understanding of memory-mapped I/O, linker scripts, and cross-compilation toolchains (GCC/Clang/ARM toolchains).
  • Hands-on experience developing and debugging low-level peripheral drivers (SPI, I2C, UART, DMA, timers/counters, GPIO) on ARM Cortex-M (or similar) microcontrollers/SoCs.
  • Practical experience with one or more RTOS environments (FreeRTOS, Zephyr, ThreadX, embOS, or equivalent): task scheduling, semaphores/mutexes, queues, priority inversion handling, and interrupt-to-task signaling.
  • Good knowledge of wireless/RF concepts and the firmware stack of Ultra-Wideband (UWB MAC/UCI) or other wireless technologies such as BLE/BT, Wi-Fi, LoRa: packet framing and detection, channel estimation, gain/calibration control, and precise TX/RX timing.
  • Experience reading digital hardware specifications (register maps, timing diagrams, finite state machine descriptions) and translating them into correct firmware sequencing, error handling.
  • Familiarity with debug tools: JTAG/SWD probes, logic analyzers, protocol analyzers, and RTL simulation/emulation environments (e.g., HAPS, Verilog/SystemVerilog testbenches) for pre-silicon firmware bring-up.
  • Understanding of low-power design techniques: clock gating, power domain sequencing, sleep/wake state management.
  • Good experience in design flows; self-motivated, flexible, good interpersonal and communication skills, a good team player able to work with cross-functional teams.
  • Strong debugging and analytical skills; comfortable working directly from RTL/architecture documentation when driver behavior is undocumented at the firmware level.

 

Key Responsibilities

  • Develop and maintain low-level drivers for UWB radio/PHY hardware: analog front-end and RF chain sequencing, receiver/transmitter enablement, calibration routines, and low level firmware development.
  • Implement product and component requirements and ensure requirement-based development and traceability against firmware/software architecture and designs.
  • Bring up and validate firmware against RTL/simulation models and silicon, working closely with digital design and DV teams to interpret register maps, timing diagrams, and hardware behavior specifications.
  • Implement ranging and positioning protocol firmware in line with the IEEE 802.15.4 UWB PHY/MAC standard: packet exchange sequencing, timed measurement/ranging exchanges, angle-of-arrival processing, and support for the standard’s various PHY operating modes.
  • Port and integrate firmware onto an RTOS (e.g., FreeRTOS, Zephyr, ThreadX) or bare-metal environment: task/thread partitioning, ISR design, DMA and interrupt-driven I/O, power-mode/sleep management, and inter-process communication (IPC) between PHY, MAC, and application layers.
  • Write board support package (BSP) code: clock/reset configuration, GPIO, SPI/I2C/UART peripheral drivers, memory-mapped register access, and bootloader/flash integration.
  • Debug hardware/firmware issues using JTAG/SWD debuggers, logic analyzers, oscilloscopes, and on-chip trace & debug facilities.
  • Collaborate with algorithm/DSP teams to integrate ranging, positioning, and sensing algorithms into real-time firmware with strict latency/timing budgets.
  • Contribute to unit test frameworks, HAL example applications, and automated regression/qualification test suites (Packet Error Rate, calibration routines).
  • Participate in design/code reviews and produce clear technical documentation (programmer’s models, FSM references, driver specs).

Skill Requirements

Other Requirements

Frequently Asked Questions

Is the salary disclosed for the Senior Technical Architect position at HCLTech?
The salary for this Senior Technical Architect role at HCLTech is not publicly listed. Click "Apply Now" to learn more about the compensation package on their official careers page.
Where is the Senior Technical Architect position at HCLTech located?
This Senior Technical Architect role at HCLTech is based in Bangalore, India. The position is listed as on-site or hybrid. Check the full job description or apply directly to confirm the work arrangement.
How do I apply for the Senior Technical Architect position at HCLTech?
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When was the Senior Technical Architect job at HCLTech posted?
This Senior Technical Architect position at HCLTech was posted on Oct 5, 2026. Apply as soon as possible — early applications are often reviewed first.
Senior Technical Architect
HCLTech
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