Senior Group Technical Architect

Job Summary

Standard Cell Characterization Architect/Manager to Lead a project and independently drive complete end to end project, ensuring high-quality execution and timely delivery. The role involves the training & Mentoring junior engineers in ramp-up. Co-ordinate effectively with the customer & team-members, for the successful overall project execution. 

Key Responsibilities 

Provide technical leadership to a project and be responsible for overall delivery. 

Independently develop standard cell library (Onsite/Offshore), including:  

Floorplanning as per area and top-level constraints 

Parasitic-aware routing 

Physical verification and sign-off 

Ensure on-time delivery of layouts with required quality standards 

Perform and debug physical verification checks (DRC, LVS, ERC, boundary conditions) 

Collaborate effectively with customers and cross-functional teams for successful project execution 

Guide and mentor junior team members, review their work and drive quality improvements 

Contribute to project planning, tracking, and execution efficiency 

Required Skills (Must-Have) 

Should be able to provide Technical Leadership for a project. 

Should be able to setup flow from scratch and mentor team members 

Strong understanding of CMOS and FinFET devices (characteristics, challenges, constraints) 

Good knowledge of digital circuit design (combinational & sequential circuits) 

Hands-on experience in:  

Standard Cell Layout Design (CMOS & FinFET) 

Physical verification flows (DRC, LVS, ERC, boundary checks) and debugging 

Expertise in:  

Floorplanning, routing, and verification of standard cell libraries 

EDA tools: Cadence Virtuoso XL, Calibre, PVS 

Proficient in Cadence Virtuoso layout editor and associated PV flow 

Good understanding of:  

Standard cell schematics 

Standard cell architectures 

Basic exposure to scripting (SKILL / Shell / Perl / Python) 

Desired Skills (Good-to-Have) 

Experience in advanced technology nodes (<16nm / FinFET nodes) 

Strong team collaboration and coordination skills across multiple teams 

Good written and verbal communication skills 

Positive attitude toward learning and adaptability 

Education & Experience 

B.Tech / M.Tech in Electronics / VLSI / Related field with 12–15 years of industry experience 

Keywords 

Standard Cell Design, Layout Design, Physical Verification, Cadence Virtuoso XL, Calibre, Characterization, View Generation, CMOS, FinFE

Key Responsibilities

Skill Requirements

Other Requirements