Java Backend Engineer
inetum2
Senior Director, Physical Design & Backend Engineering (HPC)
hophr· Software Engineer
About this role
The Senior Director, Physical Design & Backend Engineering is accountable for end-to-end backend execution across HPC SoC and MCU programs, including implementation, signoff, and convergence from RTL to GDS.
This role leads globally distributed engineering teams and ensures delivery of high-quality silicon on schedule, meeting defined power, performance, and area (PPA) targets. The role operates at the intersection of execution, technology enablement, and organizational leadership, driving consistency, scalability, and reliability across multiple sites and concurrent programs.
What you'll do
1. End-to-End Backend Execution
• Own full lifecycle delivery from RTL through physical implementation, signoff, and tape-out.
• Ensure predictable execution, design closure, and milestone adherence across all programs.
• Drive first-pass silicon success through robust methodologies and execution discipline.
• Own full lifecycle delivery from RTL through physical implementation, signoff, and tape-out.
• Ensure predictable execution, design closure, and milestone adherence across all programs.
• Drive first-pass silicon success through robust methodologies and execution discipline.
2. Global Team Leadership
• Lead and scale large, geographically distributed backend engineering teams.
• Establish clear accountability, performance standards, and delivery ownership across sites.
• Build organizational capability to support multiple concurrent SoC and MCU programs.
• Lead and scale large, geographically distributed backend engineering teams.
• Establish clear accountability, performance standards, and delivery ownership across sites.
• Build organizational capability to support multiple concurrent SoC and MCU programs.
3. PPA and Quality Accountability
• Own delivery against defined power, performance, and area (PPA) targets.
• Drive continuous improvement in cost, quality, and engineering efficiency.
• Ensure adherence to quality standards, signoff criteria, and validation requirements.
• Own delivery against defined power, performance, and area (PPA) targets.
• Drive continuous improvement in cost, quality, and engineering efficiency.
• Ensure adherence to quality standards, signoff criteria, and validation requirements.
4. Technology and Methodology Enablement
• Enable adoption of advanced process nodes and associated design methodologies.
• Drive improvements in tools, flows, and engineering practices across implementation and signoff.
• Partner with foundries, EDA vendors, and internal teams to enhance design outcomes.
• Enable adoption of advanced process nodes and associated design methodologies.
• Drive improvements in tools, flows, and engineering practices across implementation and signoff.
• Partner with foundries, EDA vendors, and internal teams to enhance design outcomes.
5. Cross-Functional Collaboration
• Partner with architecture, RTL, DFT, methodology, and product engineering teams.
• Ensure alignment between architectural intent and physical implementation feasibility.
• Support program execution through close collaboration with program and product leadership.
• Partner with architecture, RTL, DFT, methodology, and product engineering teams.
• Ensure alignment between architectural intent and physical implementation feasibility.
• Support program execution through close collaboration with program and product leadership.
6. Organizational Execution and Scaling
• Standardize ways of working across global teams to reduce variability and improve predictability.
• Drive data-driven execution using metrics, KPIs, and performance tracking.
• Identify and remove bottlenecks impacting delivery timelines or quality.
• Standardize ways of working across global teams to reduce variability and improve predictability.
• Drive data-driven execution using metrics, KPIs, and performance tracking.
• Identify and remove bottlenecks impacting delivery timelines or quality.
Scope and Impact
• Responsible for backend execution across multiple SoC and MCU programs.
• Direct leadership of large, multi-site engineering teams.
• Critical impact on silicon delivery timelines, product quality, and business outcomes.
• Key contributor to organizational execution capability and scalability within HPC.
• Responsible for backend execution across multiple SoC and MCU programs.
• Direct leadership of large, multi-site engineering teams.
• Critical impact on silicon delivery timelines, product quality, and business outcomes.
• Key contributor to organizational execution capability and scalability within HPC.
What we require
Education
• Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• Master’s degree in Electrical Engineering, Computer Engineering, or related field.
Experience
• Approximately 20+ years of experience in semiconductor design, with strong focus on physical design and implementation.
• Proven experience leading large-scale, global engineering teams.
• Demonstrated track record of delivering complex SoC programs across multiple technology nodes.
• Approximately 20+ years of experience in semiconductor design, with strong focus on physical design and implementation.
• Proven experience leading large-scale, global engineering teams.
• Demonstrated track record of delivering complex SoC programs across multiple technology nodes.
Technical Expertise
• End-to-end RTL-to-GDSII flow, including synthesis, place and route, timing closure, and physical verification.
• Advanced node implementation and signoff methodologies.
• Deep understanding of SoC and MCU design and integration.
• End-to-end RTL-to-GDSII flow, including synthesis, place and route, timing closure, and physical verification.
• Advanced node implementation and signoff methodologies.
• Deep understanding of SoC and MCU design and integration.
Leadership Capabilities
• Ability to lead large, globally distributed teams in a matrixed environment.
• Strong execution focus with accountability for delivery outcomes.
• Effective cross-functional collaboration and stakeholder management.
• Data-driven decision-making and structured problem-solving.
• Ability to lead large, globally distributed teams in a matrixed environment.
• Strong execution focus with accountability for delivery outcomes.
• Effective cross-functional collaboration and stakeholder management.
• Data-driven decision-making and structured problem-solving.
Preferred Qualifications
• Experience in high-performance computing, automotive, or advanced SoC domains.
• Exposure to methodology and flow development at scale.
• Experience working across multiple geographies and cultures.
• Experience in high-performance computing, automotive, or advanced SoC domains.
• Exposure to methodology and flow development at scale.
• Experience working across multiple geographies and cultures.
Key Success Measures
• On-time delivery of silicon across programs.
• Achievement of PPA and quality targets.
• Improvement in execution predictability and cycle time.
• Organizational scalability and capability development.
• On-time delivery of silicon across programs.
• Achievement of PPA and quality targets.
• Improvement in execution predictability and cycle time.
• Organizational scalability and capability development.
Frequently Asked Questions
Is the salary disclosed for the Senior Director, Physical Design & Backend Engineering (HPC) position at hophr?
The salary for this Senior Director, Physical Design & Backend Engineering (HPC) role at hophr is not publicly listed. Click "Apply Now" to learn more about the compensation package on their official careers page.
Where is the Senior Director, Physical Design & Backend Engineering (HPC) position at hophr located?
This Senior Director, Physical Design & Backend Engineering (HPC) role at hophr is based in Austin, TX. The position is listed as on-site or hybrid. Check the full job description or apply directly to confirm the work arrangement.
Is the Senior Director, Physical Design & Backend Engineering (HPC) role at hophr full-time or part-time?
This is listed as a Full Time position. It is posted as a Senior Director, Physical Design & Backend Engineering (HPC) role in the Software Engineer department at hophr.
Which team or department does the Senior Director, Physical Design & Backend Engineering (HPC) at hophr belong to?
This Senior Director, Physical Design & Backend Engineering (HPC) position is part of the Software Engineer department at hophr. See the full job description for more information about the team structure and responsibilities.
How do I apply for the Senior Director, Physical Design & Backend Engineering (HPC) position at hophr?
Click the "Apply Now" button on this page. You will be redirected to hophr's official application portal hosted on lever where you can submit your application directly.
When was the Senior Director, Physical Design & Backend Engineering (HPC) job at hophr posted?
This Senior Director, Physical Design & Backend Engineering (HPC) position at hophr was posted on Jul 1, 2026. Apply as soon as possible — early applications are often reviewed first.
Senior Director, Physical Design & Backend Engineering (HPC)
hophr
You'll be redirected to hophr's official application page on Lever.