Senior Design Verification Engineer - Interconnect IP

nvidia· CN05 NVIDIA Shanghai WFOE
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📍 China, ShanghaiFull time

About this role

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel.

NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!

What you’ll be doing:

  • Responsible for verifying the ASIC design, architecture and micro-architecture of the GPU memory subsystem unit using advanced verification methodologies.

  • Expected to understand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.

  • Come up with test plans, tests and verification infrastructure for complex IPs/sub-systems.

  • Responsible for performance and deadlock verification of the GPU memory subsystem unit.

  • Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.

  • Perform functional coverage driven verification closure.

  • Working with architects, designers, and pre and post silicon verification teams to accomplish your tasks.

What we need to see: 

  • Master's degree or equivalent experience in Electrical/Computer Engineering or related field.

  • 5+ years of ASIC design verification experience on complex IPs, units or sub-systems.

  • Deep understanding of verification methodologies and languages: Verilog, SystemVerilog and UVM.

  • Hands-on experience across the full verification flow: testplan, tests, coverage model, testbench and BFM modeling.

  • Background in verification using random stimulus along with functional coverage and assertion-based verification methodologies.

  • Exposure to industry standard verification tools for simulation and debug.

Ways to stand out from the crowd: 

  • Experience in memory subsystem or network interconnect IP verification.

  • Experience using AI techniques (e.g. agents, prompt engineering, workflow orchestration) to improve verification workflows.

  • Good debugging and analytical skills.

  • Good communication skills,  & dream to work as a phenomenal teammate

  • Strong spoken English and cross-team coordination are significant pluses.

With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.

Frequently Asked Questions

Is the salary disclosed for the Senior Design Verification Engineer - Interconnect IP position at nvidia?
The salary for this Senior Design Verification Engineer - Interconnect IP role at nvidia is not publicly listed. Click "Apply Now" to learn more about the compensation package on their official careers page.
Where is the Senior Design Verification Engineer - Interconnect IP position at nvidia located?
This Senior Design Verification Engineer - Interconnect IP role at nvidia is based in China, Shanghai. The position is listed as on-site or hybrid. Check the full job description or apply directly to confirm the work arrangement.
Is the Senior Design Verification Engineer - Interconnect IP role at nvidia full-time or part-time?
This is listed as a Full time position. It is posted as a Senior Design Verification Engineer - Interconnect IP role in the CN05 NVIDIA Shanghai WFOE department at nvidia.
Which team or department does the Senior Design Verification Engineer - Interconnect IP at nvidia belong to?
This Senior Design Verification Engineer - Interconnect IP position is part of the CN05 NVIDIA Shanghai WFOE department at nvidia. See the full job description for more information about the team structure and responsibilities.
How do I apply for the Senior Design Verification Engineer - Interconnect IP position at nvidia?
Click the "Apply Now" button on this page. You will be redirected to nvidia's official application portal hosted on workday where you can submit your application directly.
When was the Senior Design Verification Engineer - Interconnect IP job at nvidia posted?
This Senior Design Verification Engineer - Interconnect IP position at nvidia was posted on Aug 7, 2026. Apply as soon as possible — early applications are often reviewed first.
Senior Design Verification Engineer - Interconnect IP
nvidia
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