Senior Design Lead - Physical Design

HCLTech
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📍 San Jose, United States

About this role

Job Summary

  • Experience : 7+ years 
  • BE - ECE / MTech VLSI design   
  • Exposure to TSMC 2NP/3NP is must
  • Perform end‑to‑end physical design flow:
    • Floorplanning
    • Power planning (PG grid, IR)
    • Placement & optimization
    • CTS (Clock Tree Synthesis)
    • Routing
    • Post‑route optimization
  • Achieve timing closure across all modes and corners
  • Resolve DRC, LVS, ERC and signoff violations
  • Handle low‑power design techniques:
    • Multi‑Vt, Multi‑voltage (UPF)
    • Power gating, clock gating
  • Perform physical verification and signoff:
    • STA (Primetime)
    • SI / Crosstalk
    • IR drop & EM analysis
  • Work on advanced nodes (7nm, 5nm, 3nm or below)
  • Collaborate with:
    • RTL & Micro‑architecture teams
    • DFT & Test engineers
    • Foundry and CAD teams
  • Debug complex timing, congestion, power, and variability issues
  • Drive methodology improvements and automation (scripts/flows)

Key Responsibilities

  • Experience : 7+ years 
  • BE - ECE / MTech VLSI design   
  • Exposure to TSMC 2NP/3NP is must
  • Perform end‑to‑end physical design flow:
    • Floorplanning
    • Power planning (PG grid, IR)
    • Placement & optimization
    • CTS (Clock Tree Synthesis)
    • Routing
    • Post‑route optimization
  • Achieve timing closure across all modes and corners
  • Resolve DRC, LVS, ERC and signoff violations
  • Handle low‑power design techniques:
    • Multi‑Vt, Multi‑voltage (UPF)
    • Power gating, clock gating
  • Perform physical verification and signoff:
    • STA (Primetime)
    • SI / Crosstalk
    • IR drop & EM analysis
  • Work on advanced nodes (7nm, 5nm, 3nm or below)
  • Collaborate with:
    • RTL & Micro‑architecture teams
    • DFT & Test engineers
    • Foundry and CAD teams
  • Debug complex timing, congestion, power, and variability issues
  • Drive methodology improvements and automation (scripts/flows)

Skill Requirements

  • Experience : 7+ years 
  • BE - ECE / MTech VLSI design   
  • Exposure to TSMC 2NP/3NP is must
  • Perform end‑to‑end physical design flow:
    • Floorplanning
    • Power planning (PG grid, IR)
    • Placement & optimization
    • CTS (Clock Tree Synthesis)
    • Routing
    • Post‑route optimization
  • Achieve timing closure across all modes and corners
  • Resolve DRC, LVS, ERC and signoff violations
  • Handle low‑power design techniques:
    • Multi‑Vt, Multi‑voltage (UPF)
    • Power gating, clock gating
  • Perform physical verification and signoff:
    • STA (Primetime)
    • SI / Crosstalk
    • IR drop & EM analysis
  • Work on advanced nodes (7nm, 5nm, 3nm or below)
  • Collaborate with:
    • RTL & Micro‑architecture teams
    • DFT & Test engineers
    • Foundry and CAD teams
  • Debug complex timing, congestion, power, and variability issues
  • Drive methodology improvements and automation (scripts/flows)

Other Requirements

  • Experience : 7+ years 
  • BE - ECE / MTech VLSI design   
  • Exposure to TSMC 2NP/3NP is must
  • Perform end‑to‑end physical design flow:
    • Floorplanning
    • Power planning (PG grid, IR)
    • Placement & optimization
    • CTS (Clock Tree Synthesis)
    • Routing
    • Post‑route optimization
  • Achieve timing closure across all modes and corners
  • Resolve DRC, LVS, ERC and signoff violations
  • Handle low‑power design techniques:
    • Multi‑Vt, Multi‑voltage (UPF)
    • Power gating, clock gating
  • Perform physical verification and signoff:
    • STA (Primetime)
    • SI / Crosstalk
    • IR drop & EM analysis
  • Work on advanced nodes (7nm, 5nm, 3nm or below)
  • Collaborate with:
    • RTL & Micro‑architecture teams
    • DFT & Test engineers
    • Foundry and CAD teams
  • Debug complex timing, congestion, power, and variability issues
  • Drive methodology improvements and automation (scripts/flows)

Frequently Asked Questions

Is the salary disclosed for the Senior Design Lead - Physical Design position at HCLTech?
The salary for this Senior Design Lead - Physical Design role at HCLTech is not publicly listed. Click "Apply Now" to learn more about the compensation package on their official careers page.
Where is the Senior Design Lead - Physical Design position at HCLTech located?
This Senior Design Lead - Physical Design role at HCLTech is based in San Jose, United States. The position is listed as on-site or hybrid. Check the full job description or apply directly to confirm the work arrangement.
How do I apply for the Senior Design Lead - Physical Design position at HCLTech?
Click the "Apply Now" button on this page. You will be redirected to HCLTech's official application portal hosted on successfactors where you can submit your application directly.
When was the Senior Design Lead - Physical Design job at HCLTech posted?
This Senior Design Lead - Physical Design position at HCLTech was posted on Sep 17, 2026. Apply as soon as possible — early applications are often reviewed first.
Senior Design Lead - Physical Design
HCLTech
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