RTL2GDS IC Sr. Principal Design Engineer

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📍 SAN JOSEFull time💰 USD 161K–299K

About this role

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

  • Job Description

    • The ideal candidate will be energetic, innovative and enthused with how to help customers, solve their toughest Digital Implementation problems using Cadence technology. Will drive Pre-sales and Post–sales activities at advanced nodes for Cadence Digital IC products.

  • Key Responsibilities

    • Provide technical support to Cadence customers in the areas of Digital Design Implementation & Signoff including Synthesis, Place and Route, Design Closure, and timing/power signoff
    • Guide customers on how to best utilize Cadence technologies to achieve their design goals and meet project schedules
    • Conduct technical presentations and product demonstrations
    • Drive technical evaluations/benchmarks to success
    • Work closely with R&D to enhance the tools and methodologies to meet and exceed customer’s requirements
    • Drive adoption and proliferation of Cadence tools and technologies
    • Amend and augment the flow as needed using Tcl and/or other programming skills to meet objectives and improve results/flows
    • Capture best practices and lessons learned from current evaluations/benchmarks and utilize to improve efficiency and success rate in next engagements 
    • Provide technical support, when developing business case for process improvement projects.
    • Provide mentorship to junior engineers

      

    Job Requirements

    • Requires a BS or MS or PhD in EE with/or 10-12 years industry related experience in design and EDA (Digital Implementation/Signoff)
    • Understands ASIC Design implementation process and steps
    • Strong hands-on experience with Place & Route (Innovus, ICC2, Fusion Compiler)
    • Exposure and experience with Synthesis (Genus, RTL Compiler, Design Compiler)
    • Experience with EDA tools in the IC digital implementation & signoff flows (STA tools)
    • Strong STA and SDC debugging abilities are required.
    • Low power analysis, Clock design/analysis and hands-on 7/5nm technology node experience a plus.
    • Automation skills using Perl, Tcl and shell scripting essential 
    • Strong analytical & analysis skills covering digital implementation is critical. 
    • Proven track record and experience working in a fast paced environment 
    • Excellent customer interaction & presentation skills

The annual salary range for California is $161,000 to $299,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

Frequently Asked Questions

What is the salary for the RTL2GDS IC Sr. Principal Design Engineer role at cadence?
The listed salary for this RTL2GDS IC Sr. Principal Design Engineer position at cadence is USD 161K–299K. This is an Full time role.
Where is the RTL2GDS IC Sr. Principal Design Engineer position at cadence located?
This RTL2GDS IC Sr. Principal Design Engineer role at cadence is based in SAN JOSE. The position is listed as on-site or hybrid. Check the full job description or apply directly to confirm the work arrangement.
Is the RTL2GDS IC Sr. Principal Design Engineer role at cadence full-time or part-time?
This is listed as a Full time position. It is posted as a RTL2GDS IC Sr. Principal Design Engineer role at cadence.
How do I apply for the RTL2GDS IC Sr. Principal Design Engineer position at cadence?
Click the "Apply Now" button on this page. You will be redirected to cadence's official application portal hosted on workday where you can submit your application directly.
When was the RTL2GDS IC Sr. Principal Design Engineer job at cadence posted?
This RTL2GDS IC Sr. Principal Design Engineer position at cadence was posted on Sep 24, 2026. Apply as soon as possible — early applications are often reviewed first.
RTL2GDS IC Sr. Principal Design Engineer
cadence · 💰 USD 161K–299K
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You'll be redirected to cadence's official application page on Workday.