Principle DFT Engineer

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

As a part of the Connectivity BU DFT team the suitable candidate will work on all aspects of DFT in products catering to the networking domain: DFT architecture and Testability strategy, Flow, Implementation, Verification and post-Si bring up.
Marvell's Connectivity Business Unit is the industry-leading provider of high-speed connectivity solutions powering the full range of network infrastructure — from the optics of AI GPU boards to top-of-rack optical fibers and active copper cables in data centers and their fabrics. The BU spans multiple cutting-edge product lines, including Optical Digital Signal Processing (ODSP), Active Electrical Cable (AEC), and Coherent Digital Signal Processing (CDSP), delivering solutions to enterprise, data center, service providers, and cloud customers worldwide.

You'll work closely and mentor other DFT team members for DFT features Implementation, Integration and Verification in SoC. You will also have close interaction with Logic Design/Physical design/STA/ATE teams as needed.

What You Can Expect

• Define and drive the DFT architecture and test strategy for complex IPs and SoCs, ensuring robust testability and alignment with product quality, coverage, and manufacturability goals.
• Lead the implementation and integration of Scan, ATPG, JTAG, MBIST, and Boundary Scan (BSCAN) solutions, ensuring compliance with IEEE 1149.1/1149.6 standards.
• Develop and deploy DFT features including test structures, IP-level DFT integration, ATPG fault models, test point insertion, coverage optimization, scan insertion, and MBIST implementation at both block and chip levels.
• Own and execute hierarchical DFT flows across the design hierarchy, from individual IPs through full-chip integration.
• Implement, validate, and debug DFT/DFX features, ensuring seamless integration with the overall SoC architecture.
• Generate and validate production test patterns, perform RTL and netlist verification, execute gate-level simulations (zero-delay and SDF-based), and ensure comprehensive test-mode validation.
• Develop and maintain test timing constraints, including SDC creation, test-mode timing analysis, and support for block- and chip-level STA signoff activities.
• Utilize industry-standard EDA tools for Scan, ATPG, MBIST, and JTAG implementation, verification, and debug.
• Collaborate closely with Design, Synthesis, Physical Design, STA, Validation, and Silicon Bring-up teams to resolve DFT-related issues and ensure successful project execution.
• Drive Post-Silicon bring-up, ATE debug, silicon characterization, and production ramp-up activities, enabling efficient silicon validation and productization.
• Own DFT deliverables throughout the project lifecycle, ensuring successful execution from architecture definition through tape out, silicon validation, and manufacturing release.
• Demonstrate strong ownership, accountability, and technical leadership to ensure successful tape out and post-silicon ramp-up of the project.

What We're Looking For

• Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 12+ years of experience.
• Bachelor's degree in Electronics, Electrical Engineering or related fields and 14+ years of related professional experience.
• Hands on working experience in various stages of DFT-Execution, SCAN-Insertion/MBIST/ATPG/Validation/STA/IP-DFX/Post-Silicon Bring up/Debug 
• Thorough knowledge on various DFT/Test architecture solutions and should be involved in DFT-Architecture definition of at-least couple of Designs.
• Strong fundamentals in Digital Circuit Design and Logic Design is required
• Understanding of DFT Flows and Methodologies and Experience with Cadence/Mentor/Synopsys Tool set (Genus,Modus,NCSim/DC,Tessent,Spyglass/Tmax) 
• Proven experience leading DFT activities, including technical leadership, mentoring, and guiding DFT engineers, driving successful execution across multiple projects and enabling team scalability.
• Experience owning complete DFT responsibility for one or more successful chip tapeouts, ensuring delivery of high-quality test solutions meeting coverage, quality, and schedule targets.
• Good scripting skills in Perl and Tcl for flow automation is a plus

This role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity 

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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