Senior Principal Test Engineer
asteralabs
Principal Logic Design Engineer - UALink IP/Subsystem
asteralabs· Design Engineering CCE2
About this role
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Principal Logic Design Engineer – UALink IP/Subsystem
Experience
10–15 years
Job Summary
We are looking for a Principal Logic Design Engineer with strong expertise in high-performance interconnect and SoC/IP design to lead RTL and microarchitecture development for UALink-based IP/subsystems.
Key Responsibilities
- Lead architecture and RTL development for UALink IP/subsystems.
- Translate protocol and system requirements into scalable hardware architecture.
- Design high-bandwidth, low-latency data paths and control logic.
- Develop robust mechanisms for flow control, ordering, buffering, arbitration, error handling, and reliability.
- Define interfaces between UALink and other SoC/interconnect components.
- Develop and review SystemVerilog RTL.
- Drive design optimization for performance, power, area, and latency.
- Work closely with verification, physical design, SoC integration, and firmware teams.
- Review design specifications and contribute to architectural decisions.
- Debug complex simulation and integration issues.
- Provide technical leadership and mentorship.
Required Skills
- Strong experience in RTL and microarchitecture development.
- Experience with high-speed interconnects and/or coherent fabrics.
- Strong understanding of computer architecture, networking/interconnect concepts, and data movement.
- Proficiency in SystemVerilog/Verilog.
- Strong understanding of CDC, reset architecture, performance, and hardware design methodology.
Preferred
- Direct UALink experience.
- Experience with PCIe, CXL, CCIX, CHI, Ethernet, or similar protocols.
- Experience in AI/accelerator or high-performance compute systems.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Frequently Asked Questions
Is the salary disclosed for the Principal Logic Design Engineer - UALink IP/Subsystem position at asteralabs?
The salary for this Principal Logic Design Engineer - UALink IP/Subsystem role at asteralabs is not publicly listed. Click "Apply Now" to learn more about the compensation package on their official careers page.
Where is the Principal Logic Design Engineer - UALink IP/Subsystem position at asteralabs located?
This Principal Logic Design Engineer - UALink IP/Subsystem role at asteralabs is based in Bengaluru, Karnataka, India. The position is listed as on-site or hybrid. Check the full job description or apply directly to confirm the work arrangement.
Which team or department does the Principal Logic Design Engineer - UALink IP/Subsystem at asteralabs belong to?
This Principal Logic Design Engineer - UALink IP/Subsystem position is part of the Design Engineering CCE2 department at asteralabs. See the full job description for more information about the team structure and responsibilities.
How do I apply for the Principal Logic Design Engineer - UALink IP/Subsystem position at asteralabs?
Click the "Apply Now" button on this page. You will be redirected to asteralabs's official application portal hosted on greenhouse where you can submit your application directly.
When was the Principal Logic Design Engineer - UALink IP/Subsystem job at asteralabs posted?
This Principal Logic Design Engineer - UALink IP/Subsystem position at asteralabs was posted on Sep 17, 2026. Apply as soon as possible — early applications are often reviewed first.
Principal Logic Design Engineer - UALink IP/Subsystem
asteralabs
You'll be redirected to asteralabs's official application page on Greenhouse.