Lead Logic Design Engineer
asteralabs
Lead Logic Design Engineer
asteralabs· Design Engineering CCE2
About this role
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Lead Logic Design Engineer – UALink IP/Subsystem
Experience
6–10 years
Job Summary
Lead RTL and microarchitecture development for UALink-based IP/subsystems, focusing on high-bandwidth, low-latency data movement and scalable interconnect design.
Key Responsibilities
- Lead UALink IP/subsystem RTL development.
- Translate protocol requirements into detailed microarchitecture.
- Design high-performance control and data-path logic.
- Work on buffering, arbitration, flow control, ordering, and error handling.
- Develop and review SystemVerilog RTL.
- Drive performance, area, power, and latency optimization.
- Collaborate with verification, SoC integration, and physical design teams.
- Debug complex functional and integration issues.
- Review RTL and mentor engineers.
- Support silicon debug and issue resolution.
Required Skills
- Strong RTL and microarchitecture experience.
- Experience with high-speed interconnects.
- Strong understanding of data movement, flow control, arbitration, and buffering.
- Excellent SystemVerilog/Verilog skills.
- Experience with CDC, lint, synthesis, and timing.
- Strong debugging and technical leadership skills.
Preferred
- Direct UALink experience.
- Experience with PCIe, CXL, CHI, CCIX, Ethernet, or similar technologies.
- Experience with AI/accelerator or high-performance compute SoCs.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Frequently Asked Questions
Is the salary disclosed for the Lead Logic Design Engineer position at asteralabs?
The salary for this Lead Logic Design Engineer role at asteralabs is not publicly listed. Click "Apply Now" to learn more about the compensation package on their official careers page.
Where is the Lead Logic Design Engineer position at asteralabs located?
This Lead Logic Design Engineer role at asteralabs is based in Bengaluru, Karnataka, India. The position is listed as on-site or hybrid. Check the full job description or apply directly to confirm the work arrangement.
Which team or department does the Lead Logic Design Engineer at asteralabs belong to?
This Lead Logic Design Engineer position is part of the Design Engineering CCE2 department at asteralabs. See the full job description for more information about the team structure and responsibilities.
How do I apply for the Lead Logic Design Engineer position at asteralabs?
Click the "Apply Now" button on this page. You will be redirected to asteralabs's official application portal hosted on greenhouse where you can submit your application directly.
When was the Lead Logic Design Engineer job at asteralabs posted?
This Lead Logic Design Engineer position at asteralabs was posted on Sep 10, 2026. Apply as soon as possible — early applications are often reviewed first.
Lead Logic Design Engineer
asteralabs
You'll be redirected to asteralabs's official application page on Greenhouse.