Lead Design Engineer(Virtual Solution)
About this role
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Key Responsibilities
- Design and develop system-level AVIP solutions for emulation/prototyping platforms (Palladium, Protium)
- Build and integrate Accelerated Verification IP environments for complex SoC and subsystem validation
- Develop end-to-end verification flows including:
- AVIP integration
- Testbench and system modeling
- Bare-metal / driver-level validation
- Optimize solutions for performance, scalability, and emulation efficiency
- Develop custom test cases, tools, and automation to enable advanced use models (embedded / co-emulation / hybrid flows)
- Work closely with cross-functional teams (PE, AE, customers) to debug and resolve system-level issues
- Support customer enablement, including bring-up, debug, and solution deployment
Required Qualifications
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field with at least 3 years’ experience
- Strong expertise in high-speed protocols such as:
- PCIe, CXL, AMBA, UCIe, Ethernet (at least one)
- RTL design experience (SystemVerilog / Verilog)
- C/C++ development experience for modeling, testbench, or system integration
- Hands-on experience with Palladium / Protium / FPGA / emulation platforms is strongly preferred
- Good debugging skills for complex system integration issues
Preferred Qualifications
- Experience developing or using AVIP (Accelerated VIP) solutions
- Experience with end-to-end system validation flows (simulation → emulation → prototyping)
- Knowledge of UVM and verification frameworks
- Knowledge of Qemu/Gem5 or other system emulation projects
- Experience with multi-language environments (SV + C/C++ + Python)
- Familiarity with Emulation/Prototyping flows
- Exposure to AI/ML techniques applied to verification or tooling
- Strong problem-solving skills and ability to work independently
Soft Skills
- Excellent English communication skills (both verbal and written) are required.
- Strong learning capability and adaptability to new technologies
- Ability to collaborate across global teams
- Proactive mindset in problem solving and customer engagement
We’re doing work that matters. Help us solve what others can’t.
Frequently Asked Questions
Is the salary disclosed for the Lead Design Engineer(Virtual Solution) position at cadence?
The salary for this Lead Design Engineer(Virtual Solution) role at cadence is not publicly listed. Click "Apply Now" to learn more about the compensation package on their official careers page.
Where is the Lead Design Engineer(Virtual Solution) position at cadence located?
This Lead Design Engineer(Virtual Solution) role at cadence is based in SHANGHAI. The position is listed as on-site or hybrid. Check the full job description or apply directly to confirm the work arrangement.
Is the Lead Design Engineer(Virtual Solution) role at cadence full-time or part-time?
This is listed as a Full time position. It is posted as a Lead Design Engineer(Virtual Solution) role at cadence.
How do I apply for the Lead Design Engineer(Virtual Solution) position at cadence?
Click the "Apply Now" button on this page. You will be redirected to cadence's official application portal hosted on workday where you can submit your application directly.
When was the Lead Design Engineer(Virtual Solution) job at cadence posted?
This Lead Design Engineer(Virtual Solution) position at cadence was posted on Jun 11, 2026. Apply as soon as possible — early applications are often reviewed first.
Lead Design Engineer(Virtual Solution)
cadence
You'll be redirected to cadence's official application page on Workday.