Design Verification Engineer to Staff Engineer (Unit Level Test)

sifive· SiFive International, Inc. - Taiwan Branch
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📍 Hsinchu, TaiwanFull time

About this role

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  

Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. 

Are you ready?  

To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.

Job Description:

 

The Role:

As a Design Verification Engineer, you will work with CPU designers, compiler team, performance team, and system verification team to generate the test cases automatically to fit those teams verification requirements in different perspectives. Your responsibilities will target establishing a highly scalable and reusable constrained random test bench that produces coverage driven tests.

Responsibilities:

  • Review and influence product definition and specifications from a verification perspective and collaborate closely with the design team on feature specifications, test plans, and failure analysis.

  • Develop checkers and assertions to verify the memory subsystem designs with interconnect.

  • Develop tools, test benches, and test suites (UVM, C++/C, or otherwise as needed) to execute test plans.

  • Develop and maintain an in-house Verification IP (VIP) tailored for memory subsystem and interconnect testing 

  • Write functional coverage, analyze both code and functional coverage, and close coverage holes.

Requirements:

  • At least 3+ years of recent experience with standard verification tools and methodologies (SystemVerilog/UVM, Verdi/DVE, Verilog, Makefiles, scripting languages, etc.).

  • Familiarity with the AMBA protocol is a plus.

  • Solid understanding of processor and SoC architecture, or a strong desire and ability to learn the same.

  • A thorough understanding of the high-level verification flow methodology (test plan generation, test generation, failure analysis, coverage analysis and closure).

  • Proficient in troubleshooting and possessing strong analytical capabilities.

  • Good interpersonal skills to listen to diverse points of view and influence people from different disciplines.

If you want to do incredible work and be challenged by exciting, truly innovative projects that will test the boundaries of your skills and creativity, then SiFive is the place for you!  Be proud of your work.  Do things better.  Join SiFive.  

 

Benefits

SiFive is proud to be an equal employment opportunity workplace. We offer a competitive compensation package that includes a flexible work environment, enabling our employees to work smarter and in their own way, a generous time-off policy, an employee stock option program, pension scheme and much more.

We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment.  Please contact us to request accommodation.

 

Notice to Staffing Agencies / External Recruiters:

Thank you for your interest in SiFive Inc. Please note that SiFive does not accept unsolicited resumes from external agencies unless contracted to fill a specific position. Agencies are hereby specifically directed NOT to contact SiFive employees directly in an attempt to present candidates – all applications must go through SiFive's internal recruiting team. Any third-party resume forwarded by agencies/external recruiters to a SiFive mailing address, fax machine or email address, directly to SiFive employees, or to SiFive's resume database will be considered property of SiFive Inc and treated as a direct application. This exchange does not constitute an agreement between SiFive and the agency/external recruiter. SiFive reserves the right to contact the candidate directly. Employment agencies/external recruiters will receive no compensation from SiFive or its companies.

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in:

Taiwan

Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.

Frequently Asked Questions

Is the salary disclosed for the Design Verification Engineer to Staff Engineer (Unit Level Test) position at sifive?
The salary for this Design Verification Engineer to Staff Engineer (Unit Level Test) role at sifive is not publicly listed. Click "Apply Now" to learn more about the compensation package on their official careers page.
Where is the Design Verification Engineer to Staff Engineer (Unit Level Test) position at sifive located?
This Design Verification Engineer to Staff Engineer (Unit Level Test) role at sifive is based in Hsinchu, Taiwan. The position is listed as on-site or hybrid. Check the full job description or apply directly to confirm the work arrangement.
Is the Design Verification Engineer to Staff Engineer (Unit Level Test) role at sifive full-time or part-time?
This is listed as a Full time position. It is posted as a Design Verification Engineer to Staff Engineer (Unit Level Test) role in the SiFive International, Inc. - Taiwan Branch department at sifive.
Which team or department does the Design Verification Engineer to Staff Engineer (Unit Level Test) at sifive belong to?
This Design Verification Engineer to Staff Engineer (Unit Level Test) position is part of the SiFive International, Inc. - Taiwan Branch department at sifive. See the full job description for more information about the team structure and responsibilities.
How do I apply for the Design Verification Engineer to Staff Engineer (Unit Level Test) position at sifive?
Click the "Apply Now" button on this page. You will be redirected to sifive's official application portal hosted on workday where you can submit your application directly.
When was the Design Verification Engineer to Staff Engineer (Unit Level Test) job at sifive posted?
This Design Verification Engineer to Staff Engineer (Unit Level Test) position at sifive was posted on Aug 13, 2026. Apply as soon as possible — early applications are often reviewed first.
Design Verification Engineer to Staff Engineer (Unit Level Test)
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