CAD Developer, IR, Timing and Physical Design Optimization

nvidia· CN05 NVIDIA Shanghai WFOE
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📍 China, ShanghaiFull time

About this role

ASIC-PD team is hiring both junior and senior engineers, whose work scope is physical design from RTL to GSDII: design quality check, synthesis, formal check, partitioning, constraint (for both design and process), async check, timing analysis/fixing/signoff, also all related flow. Join us, you will work together with expertise in all these areas; you will not only work for physical application, but also drive physical friendly design with all related teams: ASIC/P&R/DFT/SI/ARCH etc.; you will work for the most advanced process/technology, the biggest chip in the world.

What You’ll Be Doing

  • Invent and optimize new methods for increasing chip frequency while minimizing power consumption across a suite of internal optimization tools. 

  • Improve algorithms (in C++) for IR drop optimization, simulation

  • As with any software engineering team, we do write a lot of code, but this is broader than a typical CAD or EDA role. Instead, we as a team own the whole process from discovery and invention of new optimization opportunities, to developing solutions and working directly inside design teams to facilitate deployment.

What We Need To See

  • BS, MS, PhD in Electrical Engineering or Computer Science or equivalent experience

  • Minimum 2+ years of relevant experience in CAD software and VLSI hardware design

  • Strength in both CAD software and VLSI design

  • Understanding of VLSI IR drop optimization or simulation and related concepts, including constraints, corner, CCSP, FSDB etc.

  • Demonstrated ability in software development using C++

  • Strong communication and interpersonal skills

Ways To Stand Out From The Crowd

  • Familiarity with RedHawk and typical design flows written in Perl, Tcl, and Python.

  • C++14 or newer experience, such as lambdas and concurrency

  • Experience in high-performance software design including multithreading, distributed computing, efficient memory, and I/O use, etc.

  • Experience in IR drop optimization, calculation

Frequently Asked Questions

Is the salary disclosed for the CAD Developer, IR, Timing and Physical Design Optimization position at nvidia?
The salary for this CAD Developer, IR, Timing and Physical Design Optimization role at nvidia is not publicly listed. Click "Apply Now" to learn more about the compensation package on their official careers page.
Where is the CAD Developer, IR, Timing and Physical Design Optimization position at nvidia located?
This CAD Developer, IR, Timing and Physical Design Optimization role at nvidia is based in China, Shanghai. The position is listed as on-site or hybrid. Check the full job description or apply directly to confirm the work arrangement.
Is the CAD Developer, IR, Timing and Physical Design Optimization role at nvidia full-time or part-time?
This is listed as a Full time position. It is posted as a CAD Developer, IR, Timing and Physical Design Optimization role in the CN05 NVIDIA Shanghai WFOE department at nvidia.
Which team or department does the CAD Developer, IR, Timing and Physical Design Optimization at nvidia belong to?
This CAD Developer, IR, Timing and Physical Design Optimization position is part of the CN05 NVIDIA Shanghai WFOE department at nvidia. See the full job description for more information about the team structure and responsibilities.
How do I apply for the CAD Developer, IR, Timing and Physical Design Optimization position at nvidia?
Click the "Apply Now" button on this page. You will be redirected to nvidia's official application portal hosted on workday where you can submit your application directly.
When was the CAD Developer, IR, Timing and Physical Design Optimization job at nvidia posted?
This CAD Developer, IR, Timing and Physical Design Optimization position at nvidia was posted on Aug 3, 2026. Apply as soon as possible — early applications are often reviewed first.
CAD Developer, IR, Timing and Physical Design Optimization
nvidia
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