ASIC Design Engineer, Clocks

nvidia· CN05 NVIDIA Shanghai WFOE
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📍 China, ShanghaiFull time

About this role

The NVIDIA GPU clocks group is looking for an excellent Senior ASIC Design Engineer to join the team. The Team is responsible for crafting all aspects of GPU clocking. We collaborate with the frontend design team to understand the clocking requirements for the chip, and work with backend teams to understand the physical restrictions. The GPU clocks group architects, designs and validates the clocks RTL. The complexity of clocks RTL has increased many fold to support our features that power our product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

What you’ll be doing:

As a Clocks team member, you will collaborate with other architects, ASIC designers and verification engineers to design high frequency and low power clocks. You should be able to engage with multiple teams and design the GPU clocks to satisfy all the architectural constraints. You will need to run and enhance some in-house flow to guarantee the good quality of clocks RTL and netlist, drive the issues to close. Together with other team members, we deliver clock information to SOC verification team, timing and DFT teams. You will use Perl/Python to improve the productivity of the above teams. Collaborate with software and silicon solution team to debug GPU clock silicon bugs in our new products.

What we need to see:

  • BS or (MS preferred) in EE or equivalent experience. 2+ years of meaningful work experience.

  • Your ability to thrive in a dynamically changing environment.

  • Validated experience in RTL design (Verilog), verification and logic synthesis. Your strong coding skills in Perl or Python or other industry-standard scripting languages.

  • Deep understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a plus. Good understanding of backend flows and requirements is a plus.

  • DFT knowledge is a plus. Experience in implementing on-chip clocking networks is desirable.

  • Excellent analytical and problem-solving skills. Fluent English (both written and spoken) and excellent communication skills.

  • Good team work spirit, easy to cooperate with team members.

Frequently Asked Questions

Is the salary disclosed for the ASIC Design Engineer, Clocks position at nvidia?
The salary for this ASIC Design Engineer, Clocks role at nvidia is not publicly listed. Click "Apply Now" to learn more about the compensation package on their official careers page.
Where is the ASIC Design Engineer, Clocks position at nvidia located?
This ASIC Design Engineer, Clocks role at nvidia is based in China, Shanghai. The position is listed as on-site or hybrid. Check the full job description or apply directly to confirm the work arrangement.
Is the ASIC Design Engineer, Clocks role at nvidia full-time or part-time?
This is listed as a Full time position. It is posted as a ASIC Design Engineer, Clocks role in the CN05 NVIDIA Shanghai WFOE department at nvidia.
Which team or department does the ASIC Design Engineer, Clocks at nvidia belong to?
This ASIC Design Engineer, Clocks position is part of the CN05 NVIDIA Shanghai WFOE department at nvidia. See the full job description for more information about the team structure and responsibilities.
How do I apply for the ASIC Design Engineer, Clocks position at nvidia?
Click the "Apply Now" button on this page. You will be redirected to nvidia's official application portal hosted on workday where you can submit your application directly.
When was the ASIC Design Engineer, Clocks job at nvidia posted?
This ASIC Design Engineer, Clocks position at nvidia was posted on Aug 3, 2026. Apply as soon as possible — early applications are often reviewed first.
ASIC Design Engineer, Clocks
nvidia
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